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===Central processing unit=== {{CPUHardwareSpecs | cpu = Ricoh 5A22, based on a [[16-bit]] 65C816 core | clock_rates_ntsc = 21.47727 MHz | clock_bus_ntsc = 3.58 [[MHz]], 2.68 MHz, or 1.79 MHz | clock_rates_pal = 21.28137 MHz | clock_bus_pal = 3.55 [[MHz]], 2.66 MHz, or 1.77 MHz | bus = [[24-bit]] and [[8-bit]] address buses, 8-bit data bus | features = DMA and HDMA<br>Timed IRQ<br>Parallel I/O processing<br>Hardware multiplication and division }} The [[Central processing unit|CPU]] is a Nintendo-custom [[Ricoh 5A22|5A22]] processor, based on a 16-bit [[WDC 65816|65c816]] core. The CPU employs a variable bus speed depending on the memory region being accessed for each instruction cycle: the input clock is divided by 6, 8, or 12 to obtain the bus clock rate. Non-access cycles, most [[Memory-mapped I/O|register]] accesses, and some general accesses use the divisor of 6. WRAM accesses and other general accesses use the divisor of 8. Only the controller port serial-access registers use the divisor of 12.<ref name="anomie_memmap">{{Cite web |url=http://www.romhacking.net/docs/193/ |title=Anomie's SNES Memory Mapping Doc |accessdate=2009-02-12 |author=anomie |publisher=[http://www.romhacking.net/ Romhacking.net] |format=text }}</ref> The chip has an 8-bit data bus, controlled by two address buses. The 24-bit "Bus A" is used for general accesses, while the 8-bit "Bus B" is used for support chip registers (mainly the video and audio processors).<ref name="anomie_memmap"/> Normally only one bus is used at a time, however the built in [[direct memory access|direct memory access (DMA)]] unit places a read signal on one bus and a write signal on the other to achieve block transfer speeds of up to 2.68 MB/s.<ref group="cn">This quantity uses the standard decimal meaning of [[megabyte]]: 1000000 bytes.</ref><ref name="anomie_regs">{{Cite web |url=http://www.romhacking.net/docs/196/ |title=Anomie's Register Doc |accessdate=2007-04-21 |author=anomie |publisher=[http://www.romhacking.net/ Romhacking.net] |format=text }}</ref> The DMA unit has 8 independent channels, each of which can be used in two modes. General DMA transfers up to 64 kB<ref group="cn" name="binary prefix">Unless otherwise specified, [[kilobyte]] (kB), [[megabyte]] (MB), and [[megabit]] (Mbit) are used in the [[binary prefix|binary sense]] in this article, referring to quantities of 1024 or 1048576.</ref> in one shot, while [[Horizontal blanking interval|H-blank]] DMA (HDMA) transfers 1β4 bytes at the end of each video [[scanline]]. HDMA is typically used to change video parameters to achieve effects such as perspective, split-screen, and non-rectangular windowing without tying up the main CPU.<ref name="anomie_regs"/> The 5A22 also contains an 8-bit parallel I/O port (which was mostly unused in the SNES); controller port interface circuits, including both [[Serial communications|serial]] and [[Parallel communications|parallel]] access to controller data; a 16-bit multiplication and division unit; and circuitry for generating [[non-maskable interrupt]]s on [[Vertical blanking interval|V-blank]] and [[Interrupt request|IRQ]] interrupts on calculated screen positions.<ref name="anomie_regs"/> {{-}}
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